1. Field of the Invention
This invention relates generally to testing of semiconductor devices, and more particularly to methods for predicting reliability of semiconductor devices.
2. Description of the Related Art
In semiconductor device manufacturing, it is important for integrated circuit (IC) producers to identify potential reliability problems as early as possible in the manufacturing process. Identifying reliability problems at an early stage protects consumers from receiving unreliable products. As end-user system complexity grows, the need to identify potential problems associated with integrated circuit devices becomes even more important.
One common method used to identify problems in semiconductor devices is a burn-in (BI) test. In a burn-in process, a semiconductor device is packaged and put into a socket mounted on a PC board. The PC board is then placed in an oven at an elevated temperature (e.g., 125xc2x0 C. ambient temperature). In a process called static burn-in process, the semiconductor device is powered up but not electrically exercised, and left in the oven at the elevated temperature. In a dynamic burn-in process, on the other hand, the semiconductor device is powered up and electrically exercised in a manner in which it might operate in the field.
Conventional burn-in tests are generally used to accelerate failures latent in the semiconductor devices in order to identify defective products sooner. For example, the burn-in tests have been routinely used to detect early life failures of semiconductor devices before shipping to customers. Some devices such as memory devices will typically undergo 100 percent burn-in for a day or so prior to shipment. This means that every device is subjected to the burn-in test. It is expensive to burn-in all semiconductor devices that are made. For many devices, only a sample of the semiconductor devices may be tested by the burn-in process.
Unfortunately, a typical burn-in process is a lengthy process that requires costly infrastructures to implement. In particular, performing a burn-in test on semiconductor devices can take hundreds of hours or even thousands of hours depending on the amount of field operation the manufacturer wishes to simulate, which can translate into several weeks in time. This delays semiconductor devices from reaching the market by a substantial amount of time. In addition, burn-in tests are often expensive because they require an expensive testing infrastructure such as oven and other testing equipment. Furthermore, burn-in processes require additional handling of the semiconductor devices that can cause deleterious effects on the devices.
Thus, what is needed is a method for efficiently predicting reliability of semiconductor devices without the lengthy delay and high cost associated with conventional burn-in tests.
Broadly speaking, the present invention fills these needs by providing methods for evaluating and predicting reliability of semiconductor devices using voltage stressing. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, computer readable media, or a device. Several inventive embodiments of the present invention are described below.
In one embodiment, the present invention provides a method for predicting reliability of semiconductor devices without undergoing a burn-in process. In this method, a set of semiconductor devices is obtained for testing. Each semiconductor device is capable of being tested to measure one or more critical parameters that may indicate field failure of the associated semiconductor device. On each of the semiconductor devices, a set of electrical tests is performed to obtain a failure result for the one or more critical parameters of each of the semiconductor devices. The set of electrical tests is performed both before and after stressing each of the semiconductor devices with an elevated voltage above a normal operating voltage for the semiconductor devices. For the set of semiconductor devices, a critical parameter failure rate is determined from the electrical test results of the semiconductor devices. The failure rate indicates a probability of failure for the entire set of semiconductor devices.
In another embodiment, the present invention provides a method for evaluating a failure rate of semiconductor wafers containing a plurality of semiconductor devices. A semiconductor wafer is selected for testing. Each semiconductor device in the selected semiconductor wafer is capable of being tested for measuring one or more critical parameters that may indicate field failure of the associated semiconductor device. For each of the semiconductor devices in the selected semiconductor wafer, the associated the one or more critical parameters are measured under a normal operating voltage for the semiconductor devices. In addition, an elevated voltage above the normal operating voltage is applied to each of the semiconductor devices for a specified period of time. The one or more associated critical parameters is then measured after applying the elevated voltage. The one or more measured critical parameters are then compared to obtain a failure result when the one or more critical parameters measured after applying the elevated voltage are not approximately equal to the one or more critical parameters measured before applying the elevated voltage. For the selected semiconductor wafer, a failure rate is determined from the electrical test (e.g., wafer sort) results of the associated semiconductor devices to indicate a probability of failure for the selected semiconductor wafer.
In yet another embodiment, disclosed is a method for evaluating a failure rate of a wafer lot having a set of semiconductor wafers. Each semiconductor wafer contains a plurality of semiconductor devices. For each semiconductor wafer in the wafer lot, the method includes: (a) selecting a semiconductor wafer for testing, wherein each semiconductor device in the selected semiconductor wafer is capable of being tested for measuring one or more critical parameters that may indicate field failure of the associated semiconductor device; (b) for each of the semiconductor devices in the selected semiconductor wafer, (b1) measuring the one or more associated critical parameters under a normal operating voltage for the semiconductor devices; (b2) applying an elevated voltage above the normal operating voltage to each of the semiconductor devices for a specified period of time; (b3) measuring the one or more associated critical parameters after applying the elevated voltage; (b4) comparing the one or more measured critical parameters to obtain a failure result when the one or more critical parameters measured after applying the elevated voltage are not approximately equal to the one or more critical parameters measured before applying the elevated voltage; and (b5) determining a failure rate for the associated semiconductor wafer from the electrical test (e.g., wafer sort) results of the semiconductor devices, wherein the failure rate indicates a probability of failure for the associated semiconductor wafer; and (c) determining an overall failure rate for the wafer lot from the failure rate of the semiconductor wafers, wherein the overall failure rate indicates a probability of failure for the entire wafer lot.
Preferably, the critical parameter is a quiescent leakage current of the semiconductor devices although other electrical parameters may also have predictive value. The measurement and evaluation of critical parameters before and after voltage stressing not only serve as an effective early predictor of product operating life reliability but also substantially reduce the time in evaluating the reliability of semiconductor devices and wafers. Additionally, the use of voltage stressing in conjunction with before and after values of critical parameters allows more rapid determination of the correlation between wafer level results and assembled product reliability when performing dynamic operating life tests. Accordingly, the present invention minimizes cost and time in the manufacturing flow without potentially deleterious effects of added handling caused by conventional burn-in processes. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.